1. Field of Invention
The present invention relates to a manufacturing method for electro-optical devices and semiconductor devices, and to an electro-optical device, semiconductor device, projection-type display device, and electronic device, to which the Silicon On Insulator technique (which will be abbreviated as “SOI” hereafter) is applied, and particularly relates to manufacturing methods to manufacture electro-optical devices and semiconductor devices having excellent reliability with a high yield, and an electro-optical device and semiconductor device with excellent reliability.
2. Description of Related Art
Conventionally, the SOI technique, wherein a semiconductor layer made up of a mono-crystalline silicon layer is formed on a insulator substrate, and semiconductor devices such as transistors and so forth are formed on the semiconductor layer, has the advantage of increased speeds, low power consumption, high integration, and the like, with regard to devices, and is a technique which has been also applied to a support substrate or the like on which a thin film transistor array (which will be referred to as “TFT” hereafter) is formed in electro-optical devices (e.g., liquid crystal devices). For manufacturing electro- optical devices employing the SOI technique as described above, a semiconductor substrate having a mono-crystalline semiconductor layer made up of mono-crystalline silicon or the like is adhered onto the support substrate. The thin film mono-crystalline semiconductor layer is formed by a method of polishing or the like, and the thin film mono-crystalline semiconductor layer is formed into transistor devices to drive liquid crystals, or the like.
Also, a technique wherein semiconductor regions with different layer thickness exist together on an SOI substrate has been applied to semiconductor integrated circuit device. For example, Japanese Unexamined Patent Application Publication No. 11-74531 as described below discloses that multiple silicon layers with thickness different one from another are formed on an embedded oxide layer, and partial-depletion-type CMOS devices are formed on a thick silicon layer of the above silicon layers, and complete- depletion-type CMOS devices are formed on a thin silicon layer thereof, thereby enabling both of low leakage current and high-speed operation to be realized.
In particular, recently, related art liquid crystal devices have been manufactured wherein transistor devices making up a peripheral circuit or the like are formed on a substrate along with transistor devices to drive liquid crystals. With the liquid crystal devices as described above, a semiconductor layer, which is to be formed into transistor devices to drive liquid crystals is formed with a thickness less than that of a semiconductor layer, which is to be formed into transistor devices making up a peripheral circuit (see Japanese Unexamined Patent Application Publication No. 11-74531, for example). With the liquid crystal devices as described above, a photo-leakage current can be reduced in the transistor devices to drive liquid crystals, and in the peripheral circuit, high-speed driving of transistor devices can be realized, and off-leakage current can be reduced.
FIGS. 12A–12E are cross-sectional process diagrams which illustrate the related art manufacturing process for semiconductor devices or electro-optical devices having semiconductor layers with different thickness as described above. With the manufacture method as shown in the drawing, first of all, an SOI substrate is prepared wherein a mono- crystalline silicon layer 506 is provided on a support substrate 510 with a silicon-oxide layer 512 introduced therebetween as shown in FIG. 12A. In the manufacturing of semiconductor devices, a silicon substrate is used for the support substrate 510. In the manufacturing of electro-optical devices, a quartz substrate is used for the support substrate 510. Subsequently, as shown in FIG. 12B, a silicon-nitride layer 503 is formed at a predetermined region on the mono-crystalline silicon layer 506 on the SOI substrate.
Next, as shown in FIG. 12C, the mono-crystalline silicon layer 506 is oxidized from the surface side by thermal-oxidation. At this time, the mono-crystalline silicon layer 506 on the region on which the silicon-nitride layer 503 is formed is not oxidized. Conversely, an oxidized layer 507 is formed on the surface of the mono-crystalline silicon layer 506 on the region on which the silicon-nitride layer 503 is not formed.
Next, the silicon-nitride layer 503 and the oxidized layer 507 are removed by etching, thereby obtaining the SOI substrate with the thickness of the mono-crystalline silicon layer being partially reduced as shown in FIG. 12D.
Subsequently, the mono-crystalline silicon layer 506 of the SOI substrate shown in FIG. 12D is subjected to patterning so as to obtain an electro-optical device having mono-crystalline silicon layers (semiconductor layers) with different layer thickness as shown in FIG. 12E. As shown in FIG. 12E, a first semiconductor layer 501 with thin layer thickness, and a second semiconductor layer 508 with a layer thickness greater than that of the first semiconductor layer, are formed on the electro-optical device, and transistor devices to drive pixels are formed on the first semiconductor layer 501 of the above-described semiconductor layers, and transistor devices for a peripheral circuit are formed on the second semiconductor layer 508 thereof, thereby providing an electro-optical device wherein optical leakage is reduced on the pixel area, and a high-speed driving circuit is formed on the perimeter region, and accordingly a high-speed crystal device with excellent reliability can be configured.